ASIC/FPGA Design and Verification Engineer

Opportunity summary

Official occupation: Elektronikingeniør. Employment conditions: Almindelige vilkår. Employer CVR: 29399417. Primary career market: Green Energy & Engineering (occupation evidence). Are you a design or verification engineer with ASIC/FPGA skills, and do you have a flair for client communication? If so, then SyoSil has a great career opportunity for you. SyoSil will soon initiate a new project, for which we search for new team members to join our existing staff of 20 highly qualified ASIC engineers. We both look for seniors as well as newly graduated engineers. The project will focus on digital design and verification for an RF radio ASIC, being part of a large international multi-team project. In this project, SyoSil will assume the full responsibility of several IP blocks, from architecture definition towards RTL design and coverage driven verification closure. Design and verification will be done using SystemVerilog and UVM. The project management will be SCRUM based. We offer: A challenging role where you work closely with a highly skilled team as well as interfacing to engineers in leading international companies Access to the latest technologies and ongoing 1 …

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